FIG. 13 shows an arrangement of a single block (unit stage) of a conventional shift register.
As shown in FIG. 13, the single block SRn of the shift register includes an RS flip-flop (hereinafter referred to as “RF-FF”) 103a, two selection circuits 105a and 106a, an analog switch (hereinafter referred to as “ASW”) 108a, an N-channel MOS transistor 110a, and two inverters 112a and 113a. The LR line is supplied with a shift direction signal, and the LRB line is supplied with an inversion signal obtained by inverting the shift direction signal. The CK1 line is supplied with a first clock signal, and the CK2 is supplied with a second clock signal.
The selection circuit 105a is arranged so as to include two analog switches ASW, and includes four input terminals p, q, i, and j and an output terminal X. When the input terminals p and q are supplied with a high input and a low input, respectively, the input terminal i and the output terminal X are connected to each other, so that a signal that is inputted to the input terminal i is outputted from the output terminal X. On the other hand, when the input terminals p and q are supplied with a low input and a high input, respectively, the input terminal j and the output terminal X are connected to each other, so that a signal that is inputted to the input terminal j is outputted from the output terminal X. Similarly, the selection circuit 106a includes four input terminals p, q, i, and j, and an output terminal Y. When the input terminals p and q are supplied with a high input and a low input, respectively, the input terminal i and the output terminal Y are connected to each other, so that a signal that is inputted to the input terminal i is outputted from the output terminal Y. On the other hand, when the input terminals p and q are supplied with a low input and a high input, respectively, the input terminal j and the output terminal Y are connected to each other, so that a signal that is inputted to the input terminal j is outputted from the output terminal Y.
The ASW 108a is constituted by a P-channel transistor and an N-channel transistor, and includes two control terminals g and G and two conductive terminals T and U. When the control terminals g is supplied with a high input or the control terminal G is supplied with a low input, the two conductive terminals T and U are connected to each other. When a gate of the N-channel MOS transistor 110a is supplied with a high input, electricity is conducted between its source and drain.
It should be noted here that the input terminal i of the selection circuit 105a and the input terminal j of the selection circuit 106a, and a node Cn−1 (output of the left block) are connected to one another, and that the input terminal j of the selection circuit 105a and the input terminal i of the selection circuit 106a, and a node Cn+1 (output of the right block) are connected to one another. Further, the input terminals p and q of the selection circuit 105a are connected to the LR line and the LRB line, respectively. Similarly, the input terminals p and q of the selection circuit 106a are connected to the LR line and the LRB line, respectively.
Further, the output terminal X of the selection circuit 105a is connected to a set bar input (SB) of the RS-FF 103a via the inverter 112a, and the output terminal Y of the selection circuit 106a is connected to a reset (R) of the RS-FF 103a. Further, an output (Q) of the RS-FF 103a, the control terminal g of the ASW 108a, and an input of the inverter 113a are connected to one another. Further, an output of the inverter 113a, the control terminal G of the ASW 108a, and the gate of the MOS transistor 110a are connected to one another. Further, the source of the MOS transistor 110a is connected to Vssd (low potential); the drain of the MOS transistor 110a, a node Cn (output of the present block), and the conductive terminal U of the ASW 108a are connected to one another. The conductive terminal T of the ASW 108a is connected to the CK2 line. The RS-FF 103a has INTB that is supplied with an initial bar (INTB) signal, by which the output Q is initialized. For example, a low INTB signal causes the output Q of the RS-FF 103a to be initialized to low.
Basic operation (from t1 at which the output of the left block becomes high to t4 at which the output of the right block becomes low) of the single block SRn of the shift register will be described below with reference to a flow chart of FIG. 15. During this period, the LR line and the LRB line are supplied with a high shift direction signal and a low shift direction signal, respectively, so that a rightward shift is made. That is, a shift is made from the left block SRn−1 to the right block SRn+1 through the present block SRn.
First, since the LR line is high and the LRB line is low, the input terminals p and q of the selection circuit 105a are supplied with a high input and a low input, respectively, so that a signal that is inputted to the input terminal i is outputted from the output terminal X (=node Sn). Similarly, the input terminals p and q of the selection circuit 106a are supplied with a high input and a low input, respectively, so that a signal that is inputted to the input terminal i is outputted from the output terminal Y (=node Rn).
At t1 where the node Cn−1 receives a high output signal from the left block SRn−1, the output terminal X of the selection circuit 105a becomes high. At this time, the node Cn+1 is low, so that the output terminal Y of the selection circuit 106a remains low. Since the output terminal X is high and the output terminal Y is low, the SB and R (reset) of the RS-FF 103a are each supplied with a low input, so that the output Q of the RS-FF 103a becomes high. With this, whereas the ASW 108a is turned on (the control terminal g becomes high and the control terminal G becomes low), the MOS transistor 110a is turned off. Therefore, the node Cn is supplied with a low output signal from the CK2 line via the conductive terminals T and U of the ASW 108a. When the CK2 line becomes high afterward (between t1 and t2), the node Cn is also supplied with a high output.
Then, at t2 where the output signal from the left block SRn−1 becomes low and the node Cn−1 receives the low output signal, the output terminal X of the selection circuit 105a becomes low. At this time, the node Cn+1 remains low, so that the output terminal Y of the selection circuit 106a also remains low. Since the output terminals X and Y are low, the SB and R (reset) of the RS-FF 103a are supplied with a high input and a low input, respectively, so that the output Q of the RS-FF 103a remains as high as currently is. Therefore, the ASW 108a remains turned on and the conductive terminals T and U are connected to each other, so that the high output signal supplied from the CK2 line at t2 is outputted to the node Cn.
Then, at t3 where the output signal from the right block SRn+1 becomes high and the node Cn+1 receives with the high output signal, the output terminal Y of the selection circuit 106a becomes high. At this time, the node Cn−1 (output of the left block SRn−1) remains low, so that the output terminal X of the selection circuit 105a also remains low. Since the output terminal X remains low and the output terminal Y becomes high, the SB of the RS-FF 103a remains high and the R (reset) of the RS-FF 103a is supplied with a high input, so that the output Q of the RS-FF 103a becomes low. With this, the ASW 108a is turned off (the control terminal g becomes low and the control terminal G becomes high), so that the conductive terminals T and U are disconnected from each other. At this time, the inverter 113a causes the gate of the N-channel MOS transistor 110a to be high, so that electricity is conducted between the source and drain of the MOS transistor 110a. With this, the node Cn is supplied with Vssd (low output signal).
Then, at t4 where the output signal from the right block SRn+1 becomes low and the node Cn+1 receives the low output signal, the output terminal Y of the selection circuit 106a becomes low. At this time, the node Cn−1 (output of the left block SRn−1) remains low, so that the output terminal X of the selection circuit 105a also remains low. Since the output terminal X remains low and the output terminal Y becomes low, the SB of the RS-FF 103a remains low and the R (reset) of the SR-FF 103a is supplied with a low input, so that the output Q of the RS-FF 103a remains high. Therefore, the ASW 108a remains turned off. The conductive terminals T and U remain disconnected from each other. The MOS transistor 110a remains turned on. The node Cn continues to be supplied with Vssd (low output signal).
An arrangement of the whole shift register will be described below by using FIG. 14 with reference to the arrangement of each of the blocks. It should be noted that the shift register can switch between a rightward shift and a leftward shift.
As shown in FIG. 14, the shift register 101 includes blocks 1 through SRn−1, SRn, and SRd (dummy block).
The block SRn includes an RS flip-flop (hereinafter referred to as “RS-FF) 103a, two selection circuits 105a and 106a, an analog switch (hereinafter referred to as “ASW”) 108a, an N-channel MOS transistor 110a, two inverters 112a and 113a, and a DELAY circuit. Similarly, the block SRn−1 includes an RS flip-flop (hereinafter referred to as “RS-FF) 103b, two selection circuits 105b and 106b, an analog switch (hereinafter referred to as “ASW”) 108b, an N-channel MOS transistor 110b, and two inverters 112b and 113b. Similarly, the block SRd (dummy block) includes an RS flip-flop (hereinafter referred to as “RS-FF) 103d, two selection circuits 105d and 106d, an analog switch (hereinafter referred to as “ASW”) 108d, an N-channel MOS transistor 110d, and two inverters 112d and 113d. 
The RS-FFs (103a, 103b, 103d) are arranged in the same manner. The selection circuits (105a, 106a, 105b, 106b, 105d, 106d) are arranged in the same manner. The analog switches ASW (108a, 108b, 108d) are arranged in the same manner. The N-channel MOS transistors (110a, 110b, 110d) are arranged in the same manner. The inverters (112a, 113a, 112b, 113b, 112d, 113d) are arranged in the same manner. Furthermore, each of those blocks (SRn−1, SRn, SRd) which constitute the shift register is basically arranged in the same manner as the single block (SRn) of the shift register of FIG. 13, except for the way the input terminals i and j of the selection circuits are connected and the way the CK1 and CK2 lines are connected. In view of this, the following describes the way the blocks are connected to one another, as well as the way the input terminals i and j of the selection circuits are connected and the way the CK1 and CK2 lines are connected.
An input terminal i of the selection circuit 105b of the block SRn−1, an input terminal j of the selection circuit 106b, and an output Cn−2 (output of a block provided on the left side of the block SRn−1) are connected to one another, and an input terminal j of the selection circuit 105b, an input terminal i of the selection circuit 106b, and an output Cn of the block SRn are connected to one another. Further, the ASW 108a has a conductive terminal T connected to the CK2 line. An input terminal i of the selection circuit 105a of the block SRn, an input terminal j of the selection circuit 106a, and an output Cn−1 of the block SRn−1 are connected to one another. Further, the selection circuit 105a has an input terminal j connected to the SP line via a start pulse switch SW117, and the selection circuit 106a has an input terminal i connected to an output Cd of the block SRd. Further, the ASW 108a has a conductive terminal T connected to the CK1 line. The selection circuit 105d of the block SRd has an input terminal i connected to the output Cn of the block SRn, and has an input terminal j connected to Vssd (low potential). The selection circuit 106d has an input terminal j connected to Vdd (high potential). The selection circuit 106d has an input terminal i connected to an R (reset) of the RS-FF 103a of the block SRn via the DELAY circuit. Further, the ASW 108d has a conductive terminal T connected to the CK2 line.
The LR line is supplied with a shift direction signal. The LRB line is supplied with an inversion signal obtained by inverting the shift direction signal. The SP line is supplied with a start pulse signal. The CK1 line is supplied with a first clock signal. The CK2 line is supplied with a second clock signal. The INT line is supplied with an INT signal (for initializing each of the RS-FFs).
Operation of the whole shift register will be described below by using timing charts of FIGS. 16 and 17 with reference to the above-described arrangement of the shift register and the above-described operation of each of the blocks.
Although not shown in FIGS. 16 and 17, the initial reset is performed regardless of the shift direction. That is, when the INT line is supplied with a high INT signal, an INTB of each of the RS-FFs are supplied with a low input, so that the respective outputs (Qn−1, Qn, and Qd) of the RS-FF 103 (103a, 103b, and 103d) become low. At this time, the respective control terminals g of the ASWs 108 become low, so that the conductive terminals T and U of each of the ASWs are disconnected from each other. Therefore, each of the MOS transistors 110 is turned on, so that each of the outputs (Cn−1, Cn, and Cd) is supplied with Vssd (low output signal). After that, the INT signal is set back to low.
Described first is a case where a leftward shift is made by supplying the LR line and the LRB line with a low shift direction signal and a high shift direction signal, respectively (i.e., a case where a shift is made from the block SRn to the block SRn−1). Such a shift will be described below with reference to the timing chart of FIG. 16.
First, since the LR line is low and the LRB line is high, the input terminals p and q of the selection circuit 105a are supplied with a low input and a high input, respectively, so that a signal that is inputted to the input terminal j is outputted from the output terminal X. Similarly, the input terminals p and q of the selection circuit 106a are also supplied with a low input and a high input, respectively, so that a signal that is inputted to the input terminal j is outputted from the output terminal Y. Further, since the LR line is low and the LRB line is high, the SW 117 is on and the SW 118 is off.
At t1 where the SP line is supplied with a high start pulse signal, the start pulse signal is supplied to the block SRn via the SW 117, so that the input terminal j of the selection circuit 105a becomes high. With this, the X (Sn) of the block SRn becomes high. Since the output Cn−1 of the block SRn−1 (input terminal j of the selection circuit 106a) is low due to the initialization, the Y of the block SRn also becomes low. Since the X of the block SRn is high and the Y of the block SRn is low, the SB and reset R (Rn) of the RS-FF 103a are each supplied with a low input, so that the output Q (Qn) of the RS-FF 103a becomes high. With this, whereas the ASW 108a is turned on (the control terminal g becomes high and the control terminal G becomes low), the MOS transistor 110a is turned off. Therefore, the output Cn is supplied with a low output signal from the CK1 line via the conductive terminals T and U of the SW 108a. 
At t2 where the start pulse signal becomes low, the input terminal j of the selection circuit 105a becomes low, so that the X and Y of the block SRn become low. That is, the SB and R (reset) of the RS-FF 103a are supplied with a high input and a low input, respectively, so that the output Q of the RS-FF 103a remains as high as currently is. Therefore, the output Cn continues to be supplied with the low output signal from the CK1 line.
Then, at t3 where the (clock) signal CK1 from the CK1 line becomes high, the output Cn becomes high. With this, the input terminal j of the selection circuit 105b of the block SRn−1 becomes high. At this time, the input terminal j (output of the left block SRn−2) of the selection circuit 106b of the block SRn−1 is low due to the initialization. Therefore, the X (Sn−1) of the block SRn−1 becomes high and the Y of the block SRn−1 becomes low. The SB and reset R (Rn−1) of the RS-FF 103b are each supplied with a low input, so that the output Q (Qn−1) of the RS-FF 103b becomes high. With this, the ASW 108b is turned on, so that the output Cn−1 is supplied with a low output signal from the CK2 line.
Then, at t4 where the (clock) signal CK1 from the CK1 line becomes low, the output Cn becomes low. With this, the input terminal j of the selection circuit 105b of the block SRn−1 becomes low. Since the input terminal j of the selection circuit 106b remains low, the X (Sn−1) and Y of the block SRn−1 become low. The SB and R (reset) of the RS-FF 103b are supplied with a high input and a low input, respectively, so that the output Q (Qn−1) of the RS-FF 103b remains as high as currently is. Further, since the ASW 108b remains turned on, the output Cn−1 continues to be supplied with the low output signal from the CK2 line.
Then, at t5 where the (clock) signal CK2 from the CK2 line becomes high, the output Cn−1 becomes high. With this, the input terminal j of the selection circuit 106a of the block SRn becomes high. Since the input terminal j of the selection circuit 105a remains low, the X (Sn) of the block SRn is low and the Y of the block SRn is high. The SB and reset R (Rn) of the RS-FF 103a are each supplied with a high input, so that the output Q (Qn) of the RS-FF 103a becomes low. With this, the ASW 108a is turned off, so that the conductive terminals T and U are disconnected from each other. Meanwhile, electricity is conducted between the drain and source of the MOS transistor 110a, so that the output Cn is supplied with Vssd (low output signal).
Then, at t6 where the (clock) signal CK2 from the CK2 line is low, the output Cn−1 becomes low. With this, the input terminal j of the selection circuit 106a of the block SRn becomes low. Since the input terminal j of the selection circuit 105a remains low, the X (Sn) the block SRn is low and the Y of the block SRn becomes low. The SB and reset R (Rn) of the RS-FF 103a are supplied with a high input and a low input, respectively, so that the output Q (Qn) of the RS-FF 103a remains low. With this, the ASW 108a is turned off. Meanwhile, electricity is conducted between the source and drain of the MOS transistor 110a, so that the output Cn continues to be supplied with Vssd (low output signal).
Described next is a case where a rightward shift is made by supplying the LR line and the LRB line with a high shift direction signal and a low shift direction signal, respectively (a case where a shift is made from the block SRn−1 to the block SRd through the block SRn). Such a shift will be described below with reference to the timing chart of FIG. 17.
First, since the LR line is high and the LRB line is low, the input terminals p and q of the selection circuit 105a are supplied with a high input and a low input, respectively, so that a signal that is inputted to the input terminal i is outputted from the output terminal X. Similarly, the input terminals p and q of the selection circuit 106a are also supplied with a high input and a low input, respectively, so that a signal that is inputted to the input terminal i is outputted from the output terminal Y. Further, since the LR line is high and the LRB line is low, the SW 117 for a start pulse signal is off and the SW 118 is on.
At t1, the signal CK2 becomes high, so that the output Cn−1 of the block SRn−1 becomes high. Then, the input terminal i of the selection circuit 105a and the X (Sn) of the block SRn become high, and the input terminal i and Y of the selection circuit 106a become low. With this, the SB and reset R (Rn) of the RS-FF 103a are each supplied with a low input, so that the output Q (Qn) of the RS-FF 103a becomes high. At this time, the ASW 108a is turned on, so that the output Cn is supplied with a low output signal from the CK1 line via the conductive terminals T and U.
At t2, the signal CK1 becomes high, so that the output Cn of the block SRn becomes high. Then, the input terminal i of the selection circuit 105d of the block SRd and the X (Sd) of the block SRd become high, and the input terminal i of the selection circuit 106d and the Y of the selection circuit 106a become low. With this, the SB and reset R (Rd) of the RS-FF 103d are each supplied with a low input, so that the output Q (Qd) of the RS-FF 103d becomes high. At this time, the ASW 108d is turned on, so that the output Cd is supplied with a low output signal from the CK2 line via the conductive terminals T and U.
At t3, the signal CK2 becomes high, so that the output Cd of the block SRd becomes high. With this, the input terminal i of the selection circuit 105a of the block SRn and the X (Sn) of the block SRn are low, and the input terminal i of the selection circuit 106d and the Y of the block SRn are high. Therefore, the SB and reset R (Rn) of the RS-FF 103a are each supplied with a high input, so that the output Q of the RS-FF 103a becomes low. At this time, since the ASW 108a is off, the output Cn is supplied with Vssd (low output signal) via the source and drain of the MOS transistor 110a. It should be noted here that: the high output signal from the Y of the selection circuit 106a is delayed by the DELAY circuit, and then is inputted to the input terminal i of the selection circuit 106d at t4.
At t4, the input terminal i of the selection circuit 105d of the block SRd and the X (Sd) of the block SRd become low, and the input terminal i of the selection circuit 106d and the Y of the block SRd become high. With this, the SB and reset R (Rd) of the RS-FF 103d are each supplied with a high input, so that the output Q (Qd) of the RS-FF 103d becomes low. At this time, since the ASW 108d is off, the output Cd is supplied with Vssd (low output signal) via the source and drain of the MOS transistor 110d. 
[Patent Document 1] Japanese Unexamined Patent Application Publication No. 135093/2001 (Tokukai 2001-135093; published on May 18, 2001)
[Patent Document 2] Japanese Unexamined Patent Application Publication No. 339984/2000 (Tokukai 2000-339984; published on Dec. 8, 2000)
[Patent Document 3] Japanese Unexamined Patent Application Publication No. 307495/2001 (Tokukai 2001-307495; published on Nov. 2, 2001)
[Patent Document 4] United States Patent Application Publication No. US2003/0184512A1 (published on Oct. 2, 2003)